XRD9814 Datasheet, PDF (14/53 Pages) Exar Corporation – 3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors

XRD9814/9816
GENERAL DESCRIPTION
The XRD9814/9816 contains all of the circuitry re-
quired to create a complete 3-channel signal processor
/digitizer for use in CCD/CIS imaging systems. Each
channel includes a correlated double sampler (CDS),
programmable gain amplifier (PGA) and channel offset
adjustment. The input stage can also be configured for
use with inverting/non-inverting, AC or DC coupled
signals. In order to maximize flexibility, the specific
operating mode is programmable through two configu-
ration registers. In addition, the gain and offset of each
channel can be independently programmed through
separate gain and offset registers. Configuration
register data is loaded serially through a 3-pin serial
interface. Specific details for register writes are de-
tailed below. After signal conditioning the three PGA
outputs are digitized by a 14-bit/16-bit A/D converter.
Writing Registers Data
The XRD9814/9816 utilizes eight 10-Bit registers to
store configuration, gain and offset information. Regis-
ter data is written through the 3-pin serial interface
consisting of SDI (serial data input), SCLK (serial shift
clock) and LOAD (positive edge write enable). A write
consists of pulling LOAD low, shifting in 3 bits of
address (MSB first) and 10 bits of data (MSB first).
Data is written on the rising edge of SCLK and the last
13 bits are latched. The timing for writing to registers
is shown in Figure 17 and 18.
When INSEL=0, SCLK, SDI, and LOAD pins are active
for serial programming.
When INSEL=1, SCLK and SDI pins are inactive, and
the serial programming is done through I/O pins DB12/
DB14 and DB13/DB15 while LOAD pin is low.
Configuration Register #1
The bit assignment and definition for this register is
detailed in the Configuration Register #1 Definition
Table (Table 2). The primary purpose of this register is
to configure the analog input blocks for CCD or S/H
operation.
Clamp Mode
The clamp mode setting determines the conditions
when the internal clamp is enabled (see Table 5). The
pixel and CCD line-clamp modes are used to DC-
restore AC coupled CCD input signals to the PGA
common-mode input voltage while using correlated
double sampling. S/H line mode should be used to DC-
restore AC coupled inputs which do not utilize corre-
lated double sampling and have only one control input
(VSAMP). No-clamp mode should be used for DC
coupled S/H inputs.
Pixel Mode (CCD with CDS)
The input clamp is active each pixel period with a
pulse-width determined by the Black- level Sampling
Input (BSAMP). The position of BSAMP can be
optimized to eliminate the effects of the CCD reset
pulse. Since the input capacitor is recharged to the
clamp voltage on each pixel, common-mode droop
errors are eliminated.
CCD Line Mode (CCD with CDS)
The input clamp is enabled only at the beginning of the
line by gating BSAMP with LCLMP. Gating with
LCLMP maintains the ability to position the clamp
pulse (BSAMP) away from the CCD reset for varying
LCLMP position and width. Since the input capacitor
is clamped only at the beginning of each line a larger
input capacitor is required to satisfy the common-mode
input requirements of the analog front-end. (See Cou-
pling Capacitor Requirements.) The input buffer should
be enabled in this mode (PB1=1, Register #1).
S/H Line Mode (S/H with AC Coupling)
The S/H Line mode clamp is used to DC-restore AC
coupled inputs which do not utilize CDS. VSAMP is
used to sample and hold the input signal and LCLMP
performs the clamp function. This differs from the CDS
line and pixel modes which use BSAMP to clamp to the
reference level and VSAMP to hold the video input. The
input buffer should be enabled in this mode (PB1=1,
Register #1).
Rev. 1.00
14