XR20V2170 Datasheet, PDF (9/52 Pages) Exar Corporation – I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER

XR20V2170
REV. 1.0.0
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.2.1 SPI Bus Interface
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 5 Mbps. To access the device in the SPI
mode, the CS# signal for the V2170 is asserted by the SPI master, then the SPI master starts toggling the SCL
signal with the appropriate transaction information. The first byte sent by the SPI master includes whether it is
a read or write transaction and the UART register being accessed. See Table 3 below.
TABLE 3: SPI FIRST BYTE FORMAT
BIT
FUNCTION
7 Read/Write#
Logic 1 = Read
Logic 0 = Write
6:3 UART Internal Register Address A3:A0
2:1 UART Channel Select
’00’ = UART Channel A, other values are reserved
0 Reserved
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
2.3 Device Reset
The RESET# input resets the internal registers and the serial interface outputs in the UART to its default state
(see Table 16). An active low pulse of longer than 40 ns duration will be required to activate the reset function
in the device.
2.4 Internal Registers
The V2170 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to the industry standard ST16C550. These registers function as data
holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR),
receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR),
programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible Scratchpad Register
(SPR).
Beyond the general 16C550 features and capabilities, the V2170 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR, TXLVL, RXLVL, IODir, IOState, IOIntEna, IOControl, EFCR and DLD) that
provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, TX and RX FIFO level
counters, and programmable FIFO trigger level control. All the register functions are discussed in full detail
later in “Section 3.0, UART Internal Registers” on page 20.
2.5 IRQ# Output
The IRQ# interrupt output changes according to the operating mode and enhanced features setup. Table 4
and 5 summarize the operating behavior for the transmitter and receiver.
TABLE 4: IRQ# PIN OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
IRQ# Pin
NO
HIGH = a byte in THR
HIGH = FIFO above trigger level
LOW = THR empty
LOW = FIFO below trigger level or FIFO empty
IRQ# Pin
YES
HIGH = a byte in THR
HIGH = FIFO above trigger level
LOW = transmitter empty LOW = FIFO below trigger level or transmitter empty
9