XR20V2170 Datasheet, PDF (52/52 Pages) Exar Corporation – I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER

XR20V2170
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.0
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 23
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 23
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 24
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 24
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 24
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 25
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 25
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 26
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 27
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 28
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 28
TABLE 12: REGISTER AT ADDRESS OFFSET 0X6 ............................................................................................................................. 29
TABLE 13: REGISTER AT ADDRESS OFFSET 0X7 ............................................................................................................................. 29
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 30
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 30
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 31
4.11 TRANSMISSION CONTROL REGISTER (TCR) - READ/WRITE (REQUIRES EFR BIT-4 = 1)..................... 31
4.12 TRIGGER LEVEL REGISTER (TLR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) ...................................... 32
4.13 TRANSMIT FIFO LEVEL REGISTER (TXLVL) - READ-ONLY....................................................................... 32
4.14 RECEIVE FIFO LEVEL REGISTER (RXLVL) - READ-ONLY ......................................................................... 32
4.15 GPIO DIRECTION REGISTER (IODIR) - READ/WRITE ................................................................................. 32
4.16 GPIO STATE REGISTER (IOSTATE) = READ/WRITE................................................................................... 33
4.17 GPIO INTERRUPT ENABLE REGISTER (IOINTENA) - READ/WRITE ......................................................... 33
4.18 GPIO CONTROL REGISTER (IOCONTROL) - READ/WRITE........................................................................ 33
4.19 EXTRA FEATURES CONTROL REGISTER (EFCR) - READ/WRITE............................................................ 33
4.20 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD[3:0]) - READ/WRITE................................ 34
TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 34
4.21 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 34
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 35
4.21.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 36
TABLE 16: UART RESET STATES ............................................................................................................................................... 37
5.0 ELECTRICAL CHARACTERISTICS ...................................................................................................... 38
ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 38
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) .............................................. 38
ELECTRICAL CHARACTERISTICS ................................................................................................................... 39
AC ELECTRICAL CHARACTERISTICS - UART CLOCK ..................................................................................... 40
FIGURE 15. CLOCK TIMING............................................................................................................................................................. 40
AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS ........................................................ 41
FIGURE 16. SCL DELAY AFTER RESET........................................................................................................................................... 42
FIGURE 17. I2C-BUS TIMING DIAGRAM .......................................................................................................................................... 42
FIGURE 18. WRITE TO OUTPUT...................................................................................................................................................... 42
FIGURE 19. MODEM INPUT PIN INTERRUPT ..................................................................................................................................... 43
FIGURE 20. GPIO PIN INTERRUPT.................................................................................................................................................. 43
FIGURE 21. RECEIVE INTERRUPT.................................................................................................................................................... 44
FIGURE 22. RECEIVE INTERRUPT CLEAR......................................................................................................................................... 44
FIGURE 23. TRANSMIT INTERRUPT CLEAR....................................................................................................................................... 44
AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS ........................................................ 45
FIGURE 24. SPI-BUS TIMING.......................................................................................................................................................... 45
FIGURE 25. SPI WRITE MCR TO DTR OUTPUT SWITCH ................................................................................................................. 46
FIGURE 26. SPI WRITE MCR TO DTR OUTPUT SWITCH ................................................................................................................. 46
FIGURE 27. SPI WRITE THR TO CLEAR TX INT ............................................................................................................................. 47
FIGURE 28. READ MSR TO CLEAR MODEM INT.............................................................................................................................. 47
FIGURE 29. READ IOSTATE TO CLEAR GPIO INT........................................................................................................................... 48
FIGURE 30. READ RHR TO CLEAR RX INT .................................................................................................................................... 48
PACKAGE DIMENSIONS (40 PIN QFN - 6 X 6 X 0.9 mm) .............................................. 49
REVISION HISTORY...................................................................................................................................... 50
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