XR20V2170 Datasheet, PDF (19/52 Pages) Exar Corporation – I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER

XR20V2170
REV. 1.0.0
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.16 Internal Loopback
The V2170 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 14. INTERNAL LOOP BACK
Transmit Shift Register
(THR/FIFO)
VCC
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
OP1#
OP2#
CD#
TX
RX
RTS#
CTS#
DTR#
DSR#
RI#
CD#
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