XR20M1170G16-0B Datasheet, PDF (9/56 Pages) Exar Corporation – I2C/SPI UART WITH 64-BYTE FIFO

XR20M1170
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
2.1.2 SPI Bus Interface
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 18 MHz at 3.3V. To access the device in
the SPI mode, the CS# signal for the M1170 is asserted by the SPI master, then the SPI master starts toggling
the SCL signal with the appropriate transaction information. The first bit sent by the SPI master includes
whether it is a read or write transaction and the UART register being accessed. See Table 3 below.
TABLE 3: SPI FIRST BYTE FORMAT
BIT
FUNCTION
7 Read/Write#
Logic 1 = Read
Logic 0 = Write
6:3 UART Internal Register Address A3:A0
2:1 UART Channel Select
’00’ = UART Channel A, other values are reserved
0 Reserved
FIGURE 7. SPI WRITE
SCLK
SI R/W A3 A2 A1 A0 0 0 X D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 8. SPI READ
SCLK
SI R/W A3 A2 A1 A0 0 0 X
SO
D7 D6 D5 D4 D3 D2 D1 D0
The 64 byte TX FIFO can be loaded with data or 64 byte RX FIFO data can be unloaded in one SPI write or
read sequence.
FIGURE 9. SPI FIFO WRITE
SCLK
S O R/W A3 A2 A1 A0 0 0 X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
last bit
9