XR20M1170G16-0B Datasheet, PDF (18/56 Pages) Exar Corporation – I2C/SPI UART WITH 64-BYTE FIFO

XR20M1170
I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.1.0
2.12 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the M1170 compares one or two sequential receive
data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the M1170 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the M1170 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the M1170 will resume operation
and clear the flags (ISR bit-4).
Upon power-up, the contents of the Xon/Xoff 8-bit flow control registers to 0x00. The user can write any Xon/
Xoff value desired for software flow control. These registers are not reset by a hardware or software reset.
Different conditions can be set to detect Xon/Xoff characters (See Table 15) and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the M1170 compares two consecutive
receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX
transmissions accordingly. Under the above described flow control mechanisms, flow control characters are
not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the M1170 automatically
sends the Xoff-1,2 via the serial TX output to the remote modem when the RX FIFO reaches the Halt Level
(TCR[3:0]). To clear this condition, the M1170 will transmit the programmed Xon-1,2 characters as soon as RX
FIFO falls down to the Resume Level.
2.13 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The M1170 compares each incoming receive character with Xoff-2 data. If a match exists, the received data
will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the
Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of
bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison.
2.14 Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by EFCR
bit-4. It also changes the behavior of the transmit empty interrupt (see Table 4). When idle, the auto RS485
half-duplex direction control signal (RTS#) is HIGH for receive mode. When data is loaded into the THR for
transmission, the RTS# output is automatically asserted LOW prior to sending the data. After the last stop bit of
the last character that has been transmitted, the RTS# signal is automatically de-asserted. This helps in turning
around the transceiver to receive the remote station’s response. When the host is ready to transmit next polling
data packet, it only has to load data bytes to the transmit FIFO. The transmitter automatically re-asserts RTS#
(LOW) output prior to sending the data. The polarity of the RTS# output pin can be inverted by setting EFCR[5]
= 1.
2.14.1 Normal Multidrop Mode
Normal multidrop mode is enabled when EFCR bit-0 = 1 and EFR bit-5 = 0 (Special Character Detect
disabled). The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received
(parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
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