XR20M1170G16-0B Datasheet, PDF (37/56 Pages) Exar Corporation – I2C/SPI UART WITH 64-BYTE FIFO

XR20M1170
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
EFCR[6]: Reserved
EFCR[5]: Auto RS-485 Polarity Inversion
This bit changes the polarity of the Auto RS-485 Half-Duplex Direction Control output (RTS#). This bit will only
affect the behavior of the RTS# output if EFCR[4] = 1. See “Section 2.14, Auto RS485 Half-duplex Control”
on page 18 for complete details.
• Logic 0 = RTS# output is LOW when transmitting and HIGH when receiving.
• Logic 1 = RTS# output is HIGH when transmitting and LOW when receiving.
EFCR[4]: Auto RS-485 Enable
This bit enables the RTS# output as the Auto RS-485 Half-Duplex Direction Control output. See “Section
2.14, Auto RS485 Half-duplex Control” on page 18 for complete details.
• Logic 0 = RTS# output can be used for Auto RTS Hardware Flow Control or as a general purpose output.
• Logic 1 = RTS# output enabled as the Auto RS-485 Half-Duplex Direction Control output.
EFCR[3]: Reserved
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
• Logic 0 = Transmitter is enabled
• Logic 1 = Transmitter is disabled
EFCR[1] = Receiver Disable
UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in
the TSR will be received correctly and sent to the RX FIFO.
• Logic 0 = Receiver is enabled
• Logic 1 = Receiver is disabled
EFCR[0]: 9-bit or Multidrop Mode Enable
This bit enables 9-bit or Multidrop mode. See “Section 2.14, Auto RS485 Half-duplex Control” on page 18
for complete details.
• Logic 0 = Normal 8-bit mode
• Logic 1 = Enable 9-bit or Multidrop mode
4.20 Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
FRACTIONAL DIVISOR” ON PAGE 11.
DLD[5:4]: Sampling Rate Select
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