XRK7988 Datasheet, PDF (8/10 Pages) Exar Corporation – INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

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REV. P1.0.1
PRELIMINARY
XRK7988
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be
considered when analyzing the overall skew budget of a system.
HOT INSERTION AND WITHDRAWAL
In PECL applications, a powered up driver will experience a low impedance path through an XRK7988 input to
its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins
to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals.
ACQUIRING FREQUENCY LOCK
1. While the XRK7988 is receiving a valid CLK signal, assert Man_Override HIGH.
2. The PLL will phase and frequency lock within the specified lock time.
3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags.
4. De–assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode.
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