XRK7988 Datasheet, PDF (1/10 Pages) Exar Corporation – INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

xr
PRELIMINARY
XRK7988
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
MARCH 2005
GENERAL DESCRIPTION
The XRK7988 is a PLL clock driver designed
specifically for redundant clock tree designs. The
device receives two differential LVPECL clock signals
from which it generates 5 new differential LVPECL
clock outputs. Two of the output pairs regenerate the
input signals frequency and phase while the other
three pairs generate 8x, phase aligned clock outputs.
External PLL feedback is used to also provide zero
delay buffer performance.
The XRK7988 Intelligent Dynamic Clock Switch
circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW
for at least 1 period), the INP_BAD for that CLK will
be latched (H). If that CLK is the primary clock, the
REV. P1.0.1
device will switch to the good secondary clock and
phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump
caused by a failed clock is eliminated.
FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packaging
• 19.44 to 155.52 MHz
FIGURE 1. BLOCK DIAGRAM OF THE XRK7988
CLK_Selected
INP1Bad
INP0Bad
Man_Override
Alarm_Reset
Sel_CLK
Dynamic
Switch
Logic
OR
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
÷2
PLL
÷16
200-400MHz
MR
PLL_En
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com