XRK7988 Datasheet, PDF (3/10 Pages) Exar Corporation – INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

XRK7988
PRELIMINARY
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
PIN DESCRIPTIONS
xr
REV. P1.0.1
PIN NAME
CLK0, CLK0
CLK1, CLK1
Ext_FB, Ext_FB
Qa[1:0], Qa[1:0]
Qb[2:0], Qb[2:0]
Inp0bad
Inp1bad
Clk_Selected
Alarm_Reset
Sel_Clk
Manual_Override
PLL_En
MR
VCCA
VCC
GNDA
GND
TYPE
DESCRIPTION
LVPECL Input Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
LVPECL Input _{Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)}
LVPECL Input Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
LVPECL Output Differential 1x output pairs
LVPECL Output Differential 8x output pairs
LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
LVCMOS Output 0 - if clock 0 is selected
1 - if clock 1 is selected
LVCMOS Input 0 - will reset the input bad flags and align Clk_Selected with Sel_Clk. The input
is one-shotted (50KΩ pullup).
LVCMOS Input 0 - selects CLK0
1 - selects CLK1 (50kΩ pulldown)
LVCMOS Input 1 - disables internal clock switch circuitry (50KΩ pulldown).
LVCMOS Input 0 - bypasses selected input reference around the phase-locked loop (50KΩ
pullup).
LVCMOS Input 0 - resets the internal dividers forcing Q outputs LOW. Asynchronous to the
clock (50KΩ pullup).
Power Supply PLL power supply
Power Supply Digital power supply
Power Supply PLL Ground
Power Supply Digital Ground
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