XR19L222 Datasheet, PDF (8/53 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L222
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.0
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L222 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR19L222 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
R_EN
ACP
RXBSEL
PWRSAVE
FAST
UART_RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
R/W#
UART_CS#
UART_IRQ#
R_EN
ACP
RXBSEL
FAST
PWRSAVE
UART_RESET
D0
D1
VCC
D2
TXDA
D3
RXDA
D4
DTRA
D5
D6
UART
RTSA
D7
Channel A CTSA
DSRA
A0
A1
CDA
A2
RIA
IOR#
IO W #
CSA#
CSB#
INTA
INTB
UART
Channel B
R_EN
ACP
RXBSEL
PWRSAVE
FAST
RESET
TXDB
RXDB
DTRB
RTSB
CTSB
DSRB
CDB
RIB
TXB
RXB
GND
Intel Data Bus Interconnections
VCC
Full RS-232 Interface
Full RS-232 Interface
External IR or RS-422
Transceiver
VCC
VCC
(no connect)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSB#
IOR#
IOW#
CSA#
UART
Channel A
INTA
INTB
UART
Channel B
R_EN
ACP
RXBSEL
FAST
PWRSAVE
RESET
VCC
TXDA
RXDA
DTRA
RTSA
CTSA
DSRA
CDA
RIA
TXDB
RXDB
DTRB
RTSB
CTSB
DSRB
CDB
RIB
TXB
RXB
GND
Motorola Data Bus Interconnections
VCC
Full RS-232 Interface
Full RS-232 Interface
External IR or RS-422
transceiver
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