XR19L222 Datasheet, PDF (10/53 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L222
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.0
Beyond the general 16C2550 features and capabilities, the L222 offers enhanced feature registers just like the
XR16V2751, namely, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR and FC that provide automatic RTS
and CTS hardware flow control, Xon/Xoff software flow control, FIFO trigger level control and FIFO level
counters. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL
REGISTERS” on page 23.
2.7 DMA Mode
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR19L222. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
2.8 INT (IRQ#) Output
The interrupt output changes according to the operating mode and enhanced features setup. Table 3 and
Table 4 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola
modes. Also see Figures 19 through 22.
TABLE 3: INT (IRQ#) PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin 0 = one byte in THR
(I/M# = 1) 1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
IRQ# Pin 1 = one byte in THR
(I/M# = 0) 0 = THR empty
1 = FIFO above trigger level
0 = FIFO below trigger level or FIFO empty
TABLE 4: INT (IRQ#) PIN OPERATION FOR RECEIVER
INT Pin
(I/M# = 1)
IRQ# Pin
(I/M# = 0)
FCR BIT-0 = 0
(FIFO DISABLED)
0 = no data
1 = 1 byte
1 = no data
0 = 1 byte
FCR BIT-0 = 1
(FIFO ENABLED)
0 = FIFO below trigger level
1 = FIFO above trigger level
1 = FIFO below trigger level
0 = FIFO above trigger level
2.9 Crystal or External Clock Input
The L222 includes an on-chip oscillator (XTAL1 and XTAL2) to generate a clock when a crystal is connected
between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be supplied through the
XTAL1 pin. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for
other devices in the system. Please note that the input XTAL1 is not 5V tolerant and therefore, the maximum
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