XR17D158_05 Datasheet, PDF (72/73 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

XR17D158
5V PCI BUS OCTAL UART
xr
REV. 1.2.2
5.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 32
5.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 32
FIGURE 13. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 32
5.3 RECEIVER ...................................................................................................................................................... 33
5.3.1 RECEIVE HOLDING REGISTER (RHR) .................................................................................................................... 33
5.3.2 RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................... 33
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................. 33
5.3.3 RECEIVER OPERATION WITH FIFO ......................................................................................................................... 34
FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ......................................................................................... 34
5.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .............................. 34
TABLE 11: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION .......................................................................................... 34
FIGURE 16. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION...................................................................................... 35
5.5 INFRARED MODE .......................................................................................................................................... 36
FIGURE 17. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 36
5.6 INTERNAL LOOPBACK ................................................................................................................................. 37
FIGURE 18. INTERNAL LOOP BACK ................................................................................................................................................. 37
5.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING ....................................... 38
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS ................................................................................................... 38
TABLE 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 39
5.8 REGISTERS .................................................................................................................................................... 40
5.8.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 40
5.8.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 40
5.8.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE................................................................ 40
5.8.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .......................................................................................... 41
IER versus Receive FIFO Interrupt Mode Operation................................................................................................. 41
IER versus Receive/Transmit FIFO Polled Mode Operation ..................................................................................... 41
5.8.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY............................................................................................ 42
TABLE 14: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 43
5.8.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY .................................................................................................. 43
TABLE 15: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 45
5.8.7 LINE CONTROL REGISTER (LCR) - READ/WRITE .................................................................................................. 46
TABLE 16: PARITY SELECTION ........................................................................................................................................................ 47
5.8.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE ........................................................................................... 47
5.8.9 LINE STATUS REGISTER (LSR) - READ/ONLY ....................................................................................................... 48
5.8.10 MODEM STATUS REGISTER (MSR) - READ-ONLY .............................................................................................. 49
5.8.11 MODEM STATUS REGISTER (MSR) - WRITE-ONLY ............................................................................................. 50
TABLE 17: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 50
5.8.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE................................................................................................. 51
5.8.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE .................................................................................... 51
TABLE 18: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 52
5.8.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE..................................................................................... 52
TABLE 19: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 53
5.8.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ-ONLY ......................................................................... 54
5.8.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE-ONLY ........................................................................ 54
5.8.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ-ONLY ............................................................................ 54
5.8.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE-ONLY............................................................................ 54
TABLE 20: UART RESET CONDITIONS ...................................................................................................................................... 55
6.0 PROGRAMMING EXAMPLES .............................................................................................................56
6.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS .................. 56
ABSOLUTE MAXIMUM RATINGS...................................................................................57
ELECTRICAL CHARACTERISTICS ................................................................................57
DC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE ......................................................57
AC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE ......................................................58
DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE ...................................................59
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE ...................................................60
FIGURE 19. TIMING FOR EXTERNAL CLOCK INPUT AT XTAL1 PIN.................................................................................................... 61
FIGURE 20. PCI BUS CONFIGURATION SPACE REGISTERS READ AND WRITE OPERATION................................................................. 62
FIGURE 21. DEVICE CONFIGURATION AND UART REGISTERS READ OPERATION FOR A BYTE OR DWORD ...................................... 63
FIGURE 22. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND TRANSMIT DATA BURST WRITE OPERATION ..................... 64
FIGURE 23. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND RECEIVE DATA BURST READ OPERATION ........................ 65
FIGURE 24. 5V PCI BUS CLOCK (DC TO 33MHZ) .......................................................................................................................... 66
FIGURE 25. 3.3V PCI BUS CLOCK (DC TO 33MHZ) ....................................................................................................................... 67
FIGURE 26. TRANSMIT DATA INTERRUPT AT TRIGGER LEVEL ........................................................................................................... 68
FIGURE 27. RECEIVE DATA READY INTERRUPT AT TRIGGER LEVEL.................................................................................................. 68
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