XR17D158_05 Datasheet, PDF (40/73 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
xr
REV. 1.2.2
TABLE 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0 COMMENT
0 1 1 1 SPR
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 User Data
1 0 0 0 FCTR R/W
TRG
Table
Bit-1
TRG
Table
Bit-0
Auto
RS485
Enable
Invert IR RTS/DTR RTS/DTR RTS/DTR RTS/DTR
RX Input Hyst Bit-3 Hyst Bit-2 Hyst Bit-1 Hyst Bit-0
1001
EFR
R/W
Auto
Auto Special Enable Software Software Software Software
CTS/DSR RTS/DTR Char
Enable Enable Select
IER [7:5], ^{Flow Cntl Flow Cntl Flow Cntl Flow Cntl}
ISR [5:4], Bit-3
Bit-2
Bit-1
Bit-0
FCR[5:4],
MCR[7:5,2]
MSR[7:4]
1 0 1 0 TXCNT R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 0 TXTRG W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1 RXCNT R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1 RXTRG W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0 0 XCHAR R
0
0
0
0
0
0
Xon Det. Xoff Det. Self-clear
Indicator Indicator after read
1 1 0 0 XOFF1 W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 0 1 XOFF2 W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 0 XON1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 1 1 1 XON2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
NOTE: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17D158. They are present for 16C550
compatibility during Internal loopback, see Figure 18.
5.8 Registers
5.8.1 Receive Holding Register (RHR) - Read-Only
See “Section 5.3, Receiver” on page 33 for complete details.
5.8.2 Transmit Holding Register (THR) - Write-Only
See “Section 5.2, Transmitter” on page 31 for complete details.
5.8.3 Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and
receiver. The baud rate is programmed through registers DLL and DLM which are only accessible when LCR
bit-7 is set to logic 1. See “Section 5.1, Programmable Baud Rate Generator” on page 30 for more detail.
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