XRT75R03 Datasheet, PDF (71/92 Pages) Exar Corporation – THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

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THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R03
REV. 1.0.7
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02
Channel 1 Address Location = 0x0A
Channel 2 Address Location = 0x12
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of FL
Condition
Interrupt Status
Ch_n
Change of LOL
Condition
Interrupt Status
Ch_n
Change of LOS Change of DMO
Condition
Condition
nterrupt Status Interrupt Status
Ch_n
Ch_n
R/O
R/O
R/O
R/O
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-4
3
Unused
Change of FL Con-
dition Interrupt Sta-
tus
2
Change of LOL
Condition Interrupt
Status
TYPE
R/O
RUR
RUR
DEFAULT
VALUE
DESCRIPTION
0
0
Change of FL (FIFO Limit Alarm) Condition Interrupt
Status - Ch 0:
This RESET-upon-READ bit-field indicates whether or not
the Change of FL Condition Interrupt (for Channel 0) has
occurred since the last read of this register.
0 - Indicates that the Change of FL Condition Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has
occurred since the last read of this register.
NOTE:
The user can determine the current state of the
FIFO Alarm condition by reading out the contents
of Bit 3 (FL Alarm Declared) within the Alarm
Status Register.
0
Change of Receive LOL (Loss of Lock) Condition Inter-
rupt Status - Ch 0:
This RESET-upon-READ bit-field indicates whether or not
the Change of Receive LOL Condition Interrupt (for Chan-
nel 0) has occurred since the last read of this register.
0 - Indicates that the Change of Receive LOL Condition
Interrupt has NOT occurred since the last read of this reg-
ister.
1 - Indicates that the Change of Receive LOL Condition
Interrupt has occurred since the last read of this register.
NOTE:
The user can determine the current state of the
Receive LOL Defect condition by reading out the
contents of Bit 2 (Receive LOL Defect Declared)
within the Alarm Status Register.
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