XR17D158 Datasheet, PDF (71/72 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

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5V PCI BUS OCTAL UART
XR17D158
REV. 1.2.1
5.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 31
5.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 31
FIGURE 13. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 31
5.3 RECEIVER ...................................................................................................................................................... 32
5.3.1 RECEIVE HOLDING REGISTER (RHR) .................................................................................................................... 32
5.3.2 RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................... 32
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 32
5.3.3 RECEIVER OPERATION WITH FIFO......................................................................................................................... 33
FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ......................................................................................... 33
5.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .............................. 33
TABLE 11: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION .......................................................................................... 33
FIGURE 16. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION...................................................................................... 34
5.5 INFRARED MODE .......................................................................................................................................... 35
FIGURE 17. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 35
5.6 INTERNAL LOOPBACK ................................................................................................................................. 36
FIGURE 18. INTERNAL LOOP BACK ................................................................................................................................................. 36
5.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING ....................................... 37
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS ................................................................................................... 37
TABLE 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 38
5.8 REGISTERS .................................................................................................................................................... 39
5.8.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 39
5.8.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 39
5.8.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE................................................................ 39
5.8.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE.......................................................................................... 40
IER versus Receive FIFO Interrupt Mode Operation................................................................................................. 40
IER versus Receive/Transmit FIFO Polled Mode Operation ..................................................................................... 40
5.8.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY............................................................................................ 41
TABLE 14: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 42
5.8.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY.................................................................................................. 42
TABLE 15: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 44
5.8.7 LINE CONTROL REGISTER (LCR) - READ/WRITE.................................................................................................. 45
TABLE 16: PARITY SELECTION ........................................................................................................................................................ 46
5.8.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE ........................................................................................... 46
5.8.9 LINE STATUS REGISTER (LSR) - READ/ONLY ....................................................................................................... 47
5.8.10 MODEM STATUS REGISTER (MSR) - READ-ONLY .............................................................................................. 48
5.8.11 MODEM STATUS REGISTER (MSR) - WRITE-ONLY ............................................................................................. 49
TABLE 17: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 49
5.8.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE................................................................................................. 50
5.8.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE.................................................................................... 50
TABLE 18: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 51
5.8.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE..................................................................................... 51
TABLE 19: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 52
5.8.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ-ONLY ......................................................................... 53
5.8.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE-ONLY ........................................................................ 53
5.8.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ-ONLY............................................................................ 53
5.8.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE-ONLY............................................................................ 53
TABLE 20: UART RESET CONDITIONS ...................................................................................................................................... 54
6.0 PROGRAMMING EXAMPLES ............................................................................................................. 55
6.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS .................. 55
ABSOLUTE MAXIMUM RATINGS .................................................................................. 56
ELECTRICAL CHARACTERISTICS................................................................................ 56
DC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5-5.5V)
56
AC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5 - 5.5V)
57
DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 4.5 - 5.5V)
58
TA=0o to 70oC (-40o to +85oC for industrial grade package)................................................................................... 58
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 4.5 - 5.5V)
59
TA=0o to 70oC (-40o to +85oC for industrial grade package)................................................................................... 59
FIGURE 19. TIMING FOR EXTERNAL CLOCK INPUT AT XTAL1 PIN.................................................................................................... 60
FIGURE 20. PCI BUS CONFIGURATION SPACE REGISTERS READ AND WRITE OPERATION................................................................. 61
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