XR17D158 Datasheet, PDF (17/72 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

xr
REV. 1.2.1
XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
2.2.1 The Interrupt Status Register
The XR17D158 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme uses an 8-bit indicator (INT0) representing each channel
from 0 to 7. This permits the interrupt routine to quickly vector and serve that UART channel and determine the
source(s) in each individual routines. INT0 bit-0 represents the interrupt status for UART channel 0 when its
transmitter, receiver, line status, or modem port status requires service. Other bits in the INT0 register provide
indication for the other channels with bit-7 representing UART channel 7 respectively.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt
status for all 8 channels. Bits 8, 9 and 10 representing channel 0 and bits 29, 30 and 31 representing channel 7
respectively. All 8 channel interrupts status are available with a single DWORD read operation. This feature
allows the host quickly vectors and serves the interrupts, reducing service interval, hence, reduce host
bandwidth requirement. Figure 6 shows the 4-byte interrupt register and its make up.
GLOBAL INTERRUPT REGISTER (DWORD) [default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:87]
INT0 [7:0]
A special interrupt condition is generated by the D158 when it wakes up from sleep mode. This special
interrupt is cleared by reading the INT0 register. If there are not any other interrupts pending, the value read
from INT0 would be 0x00.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-7
indicates channel 7. Logic one indicates that a channel has called for service. The interrupt bit clears after
reading the appropriate register of the interrupting channel register, see Interrupt Clearing section.
The INT0 register provides individual status for each channel
INT0 Register
Individual UART Channel Interrupt Status
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
INT3, INT2 and INT1 [32:8] ]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. Bit [10:8] represent channel 0 and go up to channel 7 with bits [31:29]. The 3 bit encoding and their
priority order are shown below in Table 6. The Timer and MPIO interrupts are for the device and therefore they
exist within channel 0 space (bits [10:8]) only.
17