XR17D158 Datasheet, PDF (14/72 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
xr
REV. 1.2.1
TABLE 3: XR17D158 DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS
MEMORY SPACE
READ/WRITE
DATA WIDTH
COMMENT
0x000 - 0x00F
UART channel 0 Regs (Table 12 & Table 13) 8/16/24/32 First 8 regs are 16550 compatible
0x010 - 0x07F
Reserved
0x080 - 0x093
DEVICE CONFIG.
REGISTERS
(Table 4)
8/16/24/32
0x094 - 0x0FF Reserved
0x100 - 0x13F
UART 0 – Read FIFO
Read-Only
8/16/24/32 64 bytes of RX FIFO data
0x100 - 0x13F
UART 0 – Write FIFO
Write-Only
8/16/24/32 64 bytes of TX FIFO data
0x140 - 0x17F
Reserved
0x180 - 0x1FF
UART 0 – Read FIFO
with errors
Read-Only
16/32 64 bytes of RX FIFO data + LSR
0x200 - 0x20F
0x210 - 0x2FF
0x300 - 0x33F
0x300 - 0x33F
0x340 - 0x37F
0x380 - 0x3FF
UART channel 1 Regs (Table 12 & Table 13) 8/16//24/32 First 8 regs are 16550 compatible
Reserved
UART 1 – Read FIFO
Read-Only
8/16/24/32 64 bytes of RX FIFO data
UART 1 – Write FIFO
Write-Only
8/16/24/32 64 bytes of TX FIFO data
Reserved
UART 1 – Read FIFO
with errors
Read-Only
16/32 64 bytes of RX FIFO data + LSR
0x400 - 0x40F
0x410 - 0x4FF
0x500 - 0x53F
0x500 - 0x53F
0x540 - 0x57F
0x580 - 0x5FF
UART channel 2 Regs (Table 12 & Table 13) 8/16/24/32 First 8 regs are 16550 compatible
Reserved
UART 2 – Read FIFO
Read-Only
8/16/24/32 64 bytes of RX FIFO data
UART 2 – Write FIFO
Write-Only
8/16/24/32 64 bytes of TX FIFO data
Reserved
UART 2 – Read FIFO
with errors
Read-Only
16/32 64 bytes of RX FIFO data + LSR
0x600 - 0x60F
0x610 - 0x6FF
0x700 - 0x73F
0x700 - 0x73F
0x740 - 0x77F
0x780 - 0x7FF
UART channel 3 Regs (Table 12 & Table 13) 8/16/24/32 First 8 regs are 16550 compatible
Reserved
UART 3 – Read FIFO
Read-Only
8/16/24/32 64 bytes of RX FIFO data
UART 3 – Write FIFO
Write-Only
8/16/24/32 64 bytes of TX FIFO data
Reserved
UART 3 – Read FIFO
with errors
Read-Only
16/32 64 bytes of RX FIFO data + LSR
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