XRT75R06D Datasheet, PDF (7/105 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75R06D
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
8.5.2 Single Pointer Adjustment ................................................................................................................ 79
8.5.3 Pointer Burst ...................................................................................................................................... 79
Figure 57. Illustration of Single Pointer Adjustment Scenario ........................................................................ 79
8.5.4 Phase Transients ............................................................................................................................... 80
Figure 58. Illustration of Burst of Pointer Adjustment Scenario ...................................................................... 80
Figure 59. Illustration of "Phase-Transient" Pointer Adjustment Scenario ..................................................... 80
8.5.5 87-3 Pattern ........................................................................................................................................ 81
8.5.6 87-3 Add .............................................................................................................................................. 81
Figure 60. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ............................................... 81
8.5.7 87-3 Cancel ......................................................................................................................................... 82
Figure 61. Illustration of the 87-3 Add Pointer Adjustment Pattern ................................................................ 82
Figure 62. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................... 82
8.5.8 Continuous Pattern ............................................................................................................................ 83
8.5.9 Continuous Add ................................................................................................................................ 83
Figure 63. Illustration of Continuous Periodic Pointer Adjustment Scenario ................................................. 83
8.5.10 Continuous Cancel .......................................................................................................................... 84
Figure 64. Illustration of Continuous-Add Pointer Adjustment Scenario ......................................................... 84
Figure 65. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................... 84
8.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................................... 85
8.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM APPLICATION ...
85
8.7.1 Intrinsic Jitter Test results ................................................................................................................ 85
TABLE 20: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ....... 85
8.7.2 Wander Measurement Test Results ................................................................................................. 86
8.8 DESIGNING WITH THE LIU ................................................................................................................................. 86
8.8.1 How to design and configure the LIU to permit a system to meet the above-mentioned Intrinsic
Jitter and Wander requirements ...................................................................................................................................... 86
Figure 66. Illustration of the LIU being connected to a Mapper IC for SONET De-Sync Applications ........... 86
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 87
CHANNEL 1 ADDRESS LOCATION = 0X0E ........................................... 87
CHANNEL 2 ADDRESS LOCATION = 0X16 ........................................... 87
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 88
CHANNEL 1 ADDRESS LOCATION = 0X0E ................................................ 88
CHANNEL 2 ADDRESS LOCATION = 0X16 ................................................. 88
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ................................. 88
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................... 88
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 88
8.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to
routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU ............................................................... 89
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 89
CHANNEL 1 ADDRESS LOCATION = 0X0F .............................. 89
CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 89
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 89
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................. 89
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 89
Figure 67. Illustration of MINOR PATTERN P1 .............................................................................................. 90
Figure 68. Illustration of MINOR PATTERN P2 .............................................................................................. 91
Figure 69. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A ................................ 91
Figure 70. Illustration of MINOR PATTERN P3 .............................................................................................. 92
Figure 71. Illustration of Procedure which is used to Synthesize PATTERN B ............................................. 92
8.8.3 How does the LIU permit the user to comply with the SONET APS Recovery Time requirements
of 50ms (per Telcordia GR-253-CORE)? ......................................................................................................................... 93
Figure 72. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC .............. 93
Figure 73. Simple Illustration of the LIU being used in a SONET De-Synchronizer" Application ................... 93
TABLE 21: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ............................................ 94
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 94
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