XRT75R06D Datasheet, PDF (6/105 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.0
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................................... 45
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ......................................................................................... 46
Figure 36. Asynchronous µP Interface Signals During Programmed I/O Read and Write Operations ........... 46
Figure 37. Synchronous µP Interface Signals During Programmed I/O Read and Write Operations ............. 47
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS ........................................................................................... 47
Figure 38. Interrupt process ............................................................................................................................ 48
7.2.1 Hardware Reset: ................................................................................................................................. 49
TABLE 15: REGISTER MAP AND BIT NAMES ........................................................................................................ 49
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................ 50
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5) ...................................... 50
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N ....................................................................................... 52
8.0 THE SONET/SDH DE-SYNC FUNCTION within THE liu ................................................................. 57
8.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .......................... 57
Figure 39. A Simple Illustration of a DS3 signal being mapped into and transported over the SONET Network
58
8.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................ 59
8.2.1 HOW DS3 DATA IS MAPPED INTO SONET ...................................................................................... 59
Figure 40. A Simple Illustration of the SONET STS-1 Frame ......................................................................... 60
Figure 41. A Simple Illustration of the STS-1 Frame Structure with the TOH and the Envelope Capacity Bytes
Designated .................................................................................................................................... 61
Figure 42. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 62
Figure 43. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 63
Figure 44. Illustration of the Byte Structure of the STS-1 SPE ....................................................................... 64
Figure 45. An Illustration of Telcordia GR-253-CORE's Recommendation on how map DS3 data into an STS-1
SPE ............................................................................................................................................... 65
Figure 46. A Simplified "Bit-Oriented" Version of Telcordia GR-253-CORE's Recommendation on how to map
DS3 data into an STS-1 SPE ........................................................................................................ 65
8.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits ............................................ 66
Figure 47. A Simple Illustration of a DS3 Data-Stream being Mapped into an STS-1 SPE, via a PTE .......... 67
Figure 48. An Illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, when mapping in
a DS3 signal that has a bit rate of 44.736Mbps + 1ppm, into an STS-1 signal ............................ 68
8.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS ............................................................................................ 70
8.3.1 The Concept of an STS-1 SPE Pointer ............................................................................................. 70
Figure 49. An Illustration of the STS-1 SPE traffic that will be generated by the Source PTE, when mapping a
DS3 signal that has a bit rate of 44.736Mbps - 1ppm, into an STS-1 signal ................................ 70
Figure 50. An Illustration of an STS-1 SPE straddling across two consecutive STS-1 frames ....................... 71
8.3.2 Pointer Adjustments within the SONET Network ............................................................................ 72
Figure 51. The Bit-format of the 16-Bit Word (consisting of the H1 and H2 bytes) with the 10 bits, reflecting the
location of the J1 byte, designated ............................................................................................... 72
Figure 52. The Relationship between the Contents of the "Pointer Bits" (e.g., the 10-bit expression within the H1
and H2 bytes) and the Location of the J1 Byte within the Envelope Capacity of an STS-1 Frame ...
72
8.3.3 Causes of Pointer Adjustments ........................................................................................................ 73
Figure 53. An Illustration of an STS-1 signal being processed via a Slip Buffer ............................................. 74
Figure 54. An Illustration of the Bit Format within the 16-bit word (consisting of the H1 and H2 bytes) with the "I"
bits designated .............................................................................................................................. 75
Figure 55. An Illustration of the Bit-Format within the 16-bit word (consisting of the H1 and H2 bytes) with the
"D" bits designated ........................................................................................................................ 76
8.3.4 Why are we talking about Pointer Adjustments? ............................................................................ 77
8.4 CLOCK GAPPING JITTER ................................................................................................................................... 77
Figure 56. Illustration of the Typical Applications for the LIU in a SONET De-Sync Application .................... 77
8.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 AP-
PLICATIONS .......................................................................................................................................................................... 78
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS ..................................................................................................................................... 78
8.5.1 DS3 De-Mapping Jitter ....................................................................................................................... 79
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