XRT75R06D Datasheet, PDF (61/105 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06D
REV. 1.0.0
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
D0
SYMBOL
DESCRIPTION
DEFAULT
VALUE
JA0_n This bit along with JA1_n bit configures the Jitter
0
Attenuator as shown in the table below.
JA0_n
JA1_n
Mode
0x07 (ch 0)
0x17 (ch 1)
0x27 (ch 2)
0x37 (ch 3)
0x47 (ch 4)
0x57 (ch 5)
R/W
Jitter
Attenuator
0
0
16 bit FIFO
0
1
32 bit FIFO
1
0
Disable Jitter
Attenuator
1
1
Disable Jitter
Attenuator
D1 JATx/Rx_n Setting this bit selects the Jitter Attenuator in the
0
Transmit Path. A “0” selects in the Receive Path.
D2
JA1_n This bit along with the JA0_n configures the Jitter
0
Attenuator as shown in the table.
D3 PNTRST_n Setting this bit resets the FIFO pointers to their initial
0
state and flushes the FIFO. All existing FIFO data is
lost.
D4 DFLCK_n Set this bit to “1” to disable fast locking of the PLL.
0
This helps to reduce the time for the PLL to lock to
incoming frequency when the Jitter Attenuator
switches to narrow band.
D7-D5
Reserved
56