XRK69774 Datasheet, PDF (7/11 Pages) Exar Corporation – 1:14 LVCMOS PLL CLOCK GENERATOR

REV. P1.0.1
2.0 CONFIGURATION TABLES
PRELIMINARY
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
TABLE 6: FUNCTION CONTROLS
CONTROL PIN DEFAULT
LOGIC 0
LOGIC 1
MR/OE
1 Resets the output divide circuitry and serial Enables all outputs - normal operation
interface, tri-states all outputs
PLL_EN
1 PLL bypass mode enabled. This is a test
PLL enabled - normal operation
mode in which the reference clock is provided
to the output dividers in place of the VCO
output.
STOP_CLK
1 QA[4:0], QB[4:0] and QC[3:0] outputs disabled Outputs enabled, normal operation
in Low state.
CLK_SEL
0 CLK0 selected as PLL reference
CLK1 selected
VCO_SEL
0 VCO ÷ 2
VCO ÷ 4
TABLE 7: BANK OUTPUT DIVIDER CONTROLS
INPUT
OUTPUT
INPUT
VC0_SEL FSEL_A QA[4:0] VCO_SEL FSEL_B
0
0
÷4
0
0
0
1
÷8
0
1
1
0
÷8
1
0
1
1
÷16
1
1
OUTPUT
QB[4:0]
÷4
÷8
÷8
÷16
INPUT
VC0_SEL FSEL_C
0
0
0
1
1
0
1
1
OUTPUT
QC[3:0]
÷8
÷12
÷16
÷24
TABLE 8: FEEDBACK DIVIDER CONTROL
VCO_SEL
FSEL_FB1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FSEL_FB0
0
1
0
1
0
1
0
1
QFB
÷8
÷16
÷12
÷24
÷16
÷32
÷24
÷48
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