XRK69774 Datasheet, PDF (3/11 Pages) Exar Corporation – 1:14 LVCMOS PLL CLOCK GENERATOR

REV. P1.0.1
PIN DESCRIPTIONS
PRELIMINARY
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
PIN #
1,15, 19, 24,
30, 35, 39,
43, 47, 51
2
NAME
GND
MR/OE
3
STOP_CLK
7
FSEL_A,
4
FSEL_B,
5
FSEL_C
6
PLL_EN
8
CLK_SEL
9
CLK0
10
CLK1
11, 27, 42
12, 17, 22,
26, 28, 33,
37, 41, 45, 49
13
14
20
16, 18,21,
23, 25
29
31
NC
VDD
VDD_PLL
FSEL_FB0
FSEL_FB1
QA[4:0]
QFB
FB_IN
32, 34, 36,
38, 40
44, 46, 48, 50
52
QB[4:0]
QC[3:0]
VCO_SEL
TYPE
POWER Power supply ground
DESCRIPTION
INPUT
INPUT
INPUT
Master reset and output enable.
High = output enabled, Low = device reset & outputs tri-stated
NOTE: 25kΩ Pull-Up resistor.
Clock input for serial control
NOTE: 25kΩ Pull-Up resistor.
Select inputs for control of feedback divide value.
NOTE: Each input has a 25kΩ Pull-Down resistor.
INPUT
INPUT
INPUT
INPUT
-
POWER
PLL bypass
High = PLL Enabled. Low = PLL bypass
NOTE: 25kΩ Pull-Up resistor.
CLK0 or CLK1 Select.
High = CLK1 selected, Low = CLK0 selected
NOTE: 25kΩ Pull-Down resistor.
PLL Reference Clock Inputs
NOTE: CLK1 has 25kΩ Pull-Up resistor. CLK0 has 25kΩ Pull-Down
resistor.
NO CONNECT
Power supply
POWER
INPUT
INPUT
OUTPUT
Analog supply for PLL
Frequency Divider Select for QFB output
NOTE: Each input has a 25kΩ Pull-Down resistor.
Clock outputs (Bank A)
OUTPUT
INPUT
OUTPUT
Feedback clock output
Feedback input
NOTE: 25kΩ Pull-Up resistor.
Clock outputs (Bank B)
OUTPUT
INPUT
Clock outputs (Bank C)
VCO select. high = VCO/1, low = VCO/2.
NOTE: 25kΩ Pull-Down resistor.
3