XRK69774 Datasheet, PDF (5/11 Pages) Exar Corporation – 1:14 LVCMOS PLL CLOCK GENERATOR

REV. P1.0.1
PRELIMINARY
XRK69774
1:14 LVCMOS PLL CLOCK GENERATOR
TABLE 4: AC CHARACTERISTICS (V_DD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
CONDITION
f_REF Input reference frequency
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
f_VCO
f_MAX
VCO frequency range
Output frequency
t_PW
It_R, It_F
t_(∅)
t_SK(O)
CLKx pulse width
Input CLKx Rise/Fall time
Propagation Delay (static
phase offset)^a
Output to output skew
DC
Output duty cycle
Ot_R, Ot_F Output Rise/Fall time
t_PLZ, t_PHZ Output Disable Time
t_PZL, t_PZH Output Enable Time
t_JIT(CC) Cycle-to-Cycle Jitter Time
t_JIT(PER) Period Jitter
t_JIT(∅)
I/O Phase Jitter (rms)
VCO= 400MHz
PLL bypass mode
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
0.8V to 2.0V
CLK to FB_IN
f_REF = 50MHz & FB = ÷8
Bank A (QAx to QAy)
Bank B (QBx to QBy)
Bank C (QCx to QCy)
all outputs (QXy to QWz)
0.55 to 2.4V
All outputs @ same
frequency
All outputs @ same
frequency
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
NOTE:
a. t_(∅) = +50ps ± (1÷ (120 x f_REF)) for any reference frequency.
MIN
25.0
16.6
12.5
8.33
6.25
4.16
200
50.0
25.0
16.6
12.5
8.33
2.0
-250
47
0.1
TYP
MAX
UNIT
62.5
41.6
31.25
20.83
15.625
10.41
MHz
MHz
MHz
MHz
MHz
MHz
250
500
125
62.5
41.6
31.25
20.83
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
+100
ps
100
ps
125
ps
100
ps
175
ps
50
53
%
1.0
ns
10
ns
10
ns
90
ps
90
ps
15
ps
49
ps
18
ps
22
ps
26
ps
34
ps
5