XRK4991A Datasheet, PDF (7/13 Pages) Exar Corporation – 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

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REV. P1.0.2
PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS ⁽⁵⁾
Storage Temperature
Ambient Temperature with Power Applied
Supply Voltage to Ground
DC Input Voltage
Output Current into Outputs (LOW)
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Latch-Up Current.
–65°C to +150°C
–55°C to +125°C
–0.5V to +7.0V
–0.5V to +7.0V
64 mA
>2001V
>200 mA
NOTES:
5. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
TABLE 4: DC ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE
SYMBOL
DESCRIPTION
V_IH Input HIGH Voltage
(CLKIN, FB_IN, OE, PE)
V_IL Input LOW Voltage
(CLKIN, FB_IN, OE, PE)
V_{IHH Three-Level Input HIGH Voltage} ^[6]
V_{IMM Three-Level Input MID Voltage} ^[6]
V_{ILL Three-Level Input LOW Voltage} ^[6]
I_IN Input Leakage Current
(CLKIN and FB_IN inputs only)
I₃ 3-Level Input DC Current
(TEST, FSEL)
I_IPU Input Pull-Up Current (PE)
I_IPD Input Pull-Down Current (OE)
V_OH Output HIGH Voltage
V_OL Output LOW Voltage
MIN
2.0
V_CC-0.6
V_CC/2-0.3
MAX
UNIT
CONDITION
V_CC
V Guaranteed Logic HIGH
(CLKIN, FB_IN, OE, PE Inputs Only)
0.8
V Guaranteed Logic LOW
(CLKIN, FB_IN, OE, PE Inputs Only)
V_CC
V 3-Level Inputs Only
V_CC/2/+0.3 V 3-Level Inputs Only
0.6
V 3-Level Inputs Only
±5
µΑ V_CC = Max. V_IN = V_CC or GND
±200
µΑ V_IN = V_CC
HIGH Level
±50
µΑ V_IN = V_CC/2
MID Level
±200
µΑ V_IN = GND
LOW Level
±100
µΑ V_CC = Max
V_IN = GND
±100
µA V_CC = Max
V_IN = V_CC
2.4
V V_CC = Min., I_OH = -12mA
0.55
V V_CC = Min., I_OL = 12mA
NOTES:
6. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected
inputs to V_CC/2. If these inputs are switched (during operation), the function and timing of the outputs may be
glitched, and the PLL may require an additional t_LOCK time before all datasheet limits are achieved.
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