XRK4991A Datasheet, PDF (3/13 Pages) Exar Corporation – 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

xr
REV. P1.0.2
PIN DESCRIPTIONS
PRELIMINARY
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
PIN NAME
CLKIN
FB_IN
FSEL
SELA0
SELA1
SELB0
SELB1
SELC0
SELC1
SELD0
SELD1
TEST
OE
PE
QA0
QA1
QB0
QB1
QC0
QC1
QD0
QD1
V_CCN
V_CCQ
GND
PIN #
1
17
3
26
27
29
30
4
5
7
1
31
28
8
24
23
20
19
15
14
11
10
9
16
18
25
2
TYPE
DESCRIPTION
I Reference frequency input. This input supplies the frequency and timing against
which all functional variation is measured.
I PLL feedback input (typically connected to one of the eight outputs).
I Three-level frequency range select. Set Table 2.
I Three-level function selects inputs for output pair 1 (QA0, QA0]). Table 3.
I Three-level function selects inputs for output pair 2 (QB0, QB1). Table 3.
I Three-level function selects inputs for output pair 3 (QC0, QC1). See Table 3.
I Three-level function selects inputs for output pair 4 (QD0, QD1). See Table 3.
I Three-level select. See test mode section under the block diagram descriptions.
I Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0])
in a "Low" state - QC[1:0] may be used as the feedback signal to maintain phase
lock. When TEST is held at MID level and OE is "High", the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set OE "Low" for
normal operation.
I Selectable positive or negative edge control. When "Low"/"High" the outputs are
synchronized with the negative/positive edge of the reference clock.
O Output pair 1. See Table 2.
O Output pair 2. See Table 2.
O Output pair 3. See Table 2.
O Output pair 4. See Table 2.
PWR Power supply for output drivers.
PWR Power supply for internal circuitry.
12 PWR Ground.
13
21
22
32
3