XR19L402_09 Datasheet, PDF (7/49 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

XR19L402
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L402 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 4.
FIGURE 4. XR19L402 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR #
IOW #
UART_CSA #
UART_CSB #
UART_ INTA
UART_ INTB
R _ EN
AC P
R XBSEL
PW RSAVE
U AR T _R ESET
HALF /FULLA #
HALF /FULLB #
D0
D1
VCC3 .3
D2
D3
VCC5 .0
D4
D5
TXA +
D6
U AR T
D7
Channel A ^{RXA +}
A0
TXA -
A1
A2
R XA-
IOR #
IOW #
CSA #
CSB #
IN T A
IN T B
R _EN
AC P
R XBSEL
PW RSAVE
R ESET
U AR T
Channel B
HALF /FULLA #
HALF /FULLB #
TXB +
RXB +
TXB -
R XB-
TXB
R XB
GND
Intel Data Bus Interconnections
VCC3 .3
VC C 5.0
RS-485 Interface
RS-485 Interface
External IR or RS -232
Transceiver
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
R/W #
U AR T_ C S#
U AR T _IR Q#
R _EN
AC P
RXBSEL
PW RSAVE
U AR T _R ESET
HALF /FULLA #
HALF /FULLB #
VC C
VC C
(no connect )
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
C SB#
IOR #
IOW #
C SA#
VC C 3 .3
VC C 5 .0
U AR T
Channel A
TXA+
R XA+
TXA-
RXA -
TXB+
IN T A
IN T B
R _EN
U AR T
Channel B
ACP
R XBSEL
PW RSAVE
R ESET
HALF/FULLA #
HALF/FULLB #
R XB+
TXB -
RXB -
TXB
R XB
GND
VCC3. 3
VCC5. 0
RS-485 Interface
RS-485 Interface
External IR or RS -232
transceiver
Motorola Data Bus Interconnections
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