XR19L402_09 Datasheet, PDF (24/49 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

XR19L402
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.3
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
000
001
010
DLL RD/WR
DLM RD/WR
DLD RD/WR
Bit-7
Bit-7
0
0 0 0 DREV RD
0 0 1 DVID RD
Bit-7
0
Baud Rate Generator Divisor
Bit-6 Bit-5 Bit-4
Bit-3
Bit-6 Bit-5 Bit-4
Bit-3
0
0
0
Bit-3
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
1
Bit-2
Bit-2
Bit-2
Bit-2
0
Bit-1
Bit-1
Bit-1
Bit-1
1
Bit-0 ^LCR[7]=1
LCR ≠ 0xBF
Bit-0
Bit-0
LCR[7]=1
LCR ≠ 0xBF
EFR[4] = 1
Bit-0
0
LCR[7]=1
LCR ≠ 0xBF
DLL=0x00
DLM=0x00
Enhanced Registers
0 0 0 TRG WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
000
FC
RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
FCTR RD/WR RX/TX SCPAD
Mode Swap
Trig
Table
Bit-1
Trig
Table
Bit-0
Auto Half-
Duplex
Direction
Control
RX IR
Input
Inv.
(Ch B
Only)
Auto
RTS
Hyst
Bit-1
Auto
RTS
Hyst
Bit-0
010
EFR RD/WR Rsrvd
Rsrvd
Rsrvd
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
DLD
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
4.0 INTERNAL REGISTERS DESCRIPTION
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 14.
4.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 13.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
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