XR19L402_09 Datasheet, PDF (10/49 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

XR19L402
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.3
voltage at the pin should be 3.3V when an external clock is supplied. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 5. TYPICAL CRYSTAL CONNECTIONS
XTAL1
C1
22-47pF
XTAL2
R2
500K - 1M
R1
0-120
(Optional)
Y1
1.8432 MHz
to
24 MHz
C2
22-47pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. When VCC = 5V, the on-chip oscillator
can operate with a crystal whose frequency is not greater than 24 MHz. On the other hand, the L402 can
accept an external clock of up to 64 MHz at XTAL1 pin which results in a maximum data rate of 8 Mbps. For
further reading on the oscillator circuit please see DAN108 on EXAR’s web site at http://www.exar.com.
2.9 Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2¹⁶ - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data
bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value
of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during
initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and
the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented
and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming
the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data
rate. Table 5 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate.
If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 5. At
8X sampling rate, these data rates would double. Also, when using 8X sampling mode, please note that the bit-
time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-
standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16X mode EMSR[7] = 1
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode EMSR[7] = 0
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