XR17V252 Datasheet, PDF (67/69 Pages) Exar Corporation – 66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT

REV. 1.0.1
XR17V252
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
APPLICATIONS .............................................................................................................................................. 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XR17V252 ............................................................................................................................... 1
FIGURE 2. PIN OUT OF THE XR17V252 ........................................................................................................................................... 2
ORDERING INFORMATION ............................................................................................................................... 2
PIN DESCRIPTIONS ....................................................................................................................................... 3
PCI LOCAL BUS INTERFACE ................................................................................................................... 3
MODEM OR SERIAL I/O INTERFACE....................................................................................................... 3
ANCILLARY SIGNALS ............................................................................................................................... 4
FUNCTIONAL DESCRIPTION .......................................................................................... 6
PCI Local Bus Interface.............................................................................................................................................. 6
PCI Local Bus Configuration Space Registers ........................................................................................................... 6
Power Management Registers ................................................................................................................................... 6
EEPROM Interface ..................................................................................................................................................... 6
1.0 XR17V252 INTERNAL REGISTERS ....................................................................................................... 7
FIGURE 3. THE XR17V252 REGISTER SETS..................................................................................................................................... 7
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................... 7
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ......................................................................................................... 8
1.2 POWER MANAGEMENT REGISTERS ............................................................................................................... 9
TABLE 2: POWER MANAGEMENT REGISTERS .................................................................................................................................... 9
1.2.1 POWER STATES AND POWER STATE TRANSITIONS OF THE V252 ..................................................................... 10
D0 State ................................................................................................................................................................... 10
D3hot State .............................................................................................................................................................. 10
D3cold State ............................................................................................................................................................. 11
FIGURE 4. POWER STATE TRANSITIONS OF THE XR17V252 ........................................................................................................... 11
1.3 SPECIAL READ/WRITE REGISTER TO STORE USER INFORMATION ........................................................ 11
TABLE 3: SPECIAL READ/WRITE REGISTER ..................................................................................................................................... 11
1.4 EEPROM INTERFACE ...................................................................................................................................... 12
TABLE 4: EEPROM ADDRESS DEFINITIONS ................................................................................................................................... 12
1.5 DEVICE INTERNAL REGISTER SETS ............................................................................................................. 12
TABLE 5: XR17V252 UART AND DEVICE CONFIGURATION REGISTERS ........................................................................................... 13
1.6 DEVICE CONFIGURATION REGISTERS ......................................................................................................... 14
TABLE 6: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ................................................................................... 14
TABLE 7: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT .............................................................................. 15
1.6.1 THE GLOBAL INTERRUPT REGISTER....................................................................................................................... 15
FIGURE 5. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 .................................................................................. 16
TABLE 8: UART CHANNEL [1:0] INTERRUPT SOURCE ENCODING ..................................................................................................... 16
TABLE 9: UART CHANNEL [1:0] INTERRUPT CLEARING ................................................................................................................... 16
1.6.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-00-
00)................................................................................................................................................................................... 17
FIGURE 6. TIMER/COUNTER CIRCUIT............................................................................................................................................... 17
TABLE 10: TIMER CONTROL REGISTERS .................................................................................................................................... 18
TIMER OPERATION ................................................................................................................................................ 18
FIGURE 7. TIMER OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES .......................................................................................... 19
FIGURE 8. INTERRUPT OUTPUT (ACTIVE LOW) IN ONE-SHOT AND RE-TRIGGERABLE MODES............................................................ 20
1.6.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 20
1.6.4 REGA [15:8] RESERVED ............................................................................................................................................. 20
1.6.5 RESET [23:16] - (DEFAULT 0X00)............................................................................................................................... 20
1.6.6 SLEEP [31:24] (DEFAULT 0X00) ................................................................................................................................. 20
1.6.7 DEVICE IDENTIFICATION AND REVISION................................................................................................................. 21
1.6.8 REGB REGISTER ......................................................................................................................................................... 21
1.6.9 MULTI-PURPOSE INPUTS AND OUTPUTS ................................................................................................................ 22
1.6.10 MPIO REGISTER ........................................................................................................................................................ 22
FIGURE 9. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT........................................................................................................... 22
2.0 CRYSTAL OSCILLATOR / BUFFER..................................................................................................... 24
FIGURE 10. TYPICAL CRYSTAL CONNECTIONS ................................................................................................................................. 24
3.0 TRANSMIT AND RECEIVE DATA ........................................................................................................ 25
3.1 FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT ...................................................................... 25
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