XR17V252 Datasheet, PDF (21/69 Pages) Exar Corporation – 66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT

XR17V252
REV. 1.0.1
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power
consumption when the system needs to put the UART(s) to idle. The UART enters sleep mode when the
following conditions are satisfied after the sleep mode is enabled (LOW (default) is to disable and logic HIGH is
to enable sleep mode):
■ There is no pending interrupt
■ RX pin is idling at a HIGH in normal mode or a LOW in infrared mode
■ The modem inputs (CTS#, DSR#, CD# and RI#) are steady at either HIGH or LOW (MSR bits [3:0] =
0000)
When both UART channels are put to sleep, the on-chip oscillator shuts off to further conserve power. In this
case, the V252 is awakened by any of the following events occurring at any of the 2 UART channels:
■ A receive data start bit transition (HIGH to LOW in normal mode or from LOW to HIGH in infrared mode)
■ A data byte is loaded into the transmitter
■ A change of logic state on any of the modem inputs, i.e. any of the delta bits (MSR bits[7:4]) is set
The V252 is ready after 32 crystal clocks to ensure full functionality. Therefore, if the V252 is awakened by a
receive data start bit transition, that character (and the subsequent few characters) may not be received
correctly. Also, a special interrupt is generated with an indication of no pending interrupt. The V252 will return
to sleep mode automatically after all interrupting conditions have been serviced and cleared. It will stay in the
sleep mode of operation until it is disabled by resetting the SLEEP register bits.
1.6.7 Device Identification and Revision
There are two internal registers that provide device identification and revision, DVID and DREV registers. The
8-bit content in the DVID register provides device identification. A return value of 0x42 from this register
indicates the device is a XR17V252. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02
equals to revision B and so on. This information is very useful to the software driver for identifying which device
it is communicating with and to keep up with revision changes.
DVID [15:8]
Device identification for the type of UART. The Device ID of the XR17V252 is 0x42.
DREV [7:0]
Revision number of the XR17V252. A 0x01 represents "revision-A" with 0x02 for rev-B and so on.
REGB [23:16] (default 0x00)
REGB register provides a control for simultaneous write to both UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data in an external EEPROM.
1.6.8 REGB Register
REGB[16](Read/Write)
LOW (default) write to each UART configuration registers individually.
HIGH enables simultaneous write to both UARTs configuration register.
REGB[19:17]
Reserved
REGB[20] (Write-Only)
Control the EECK, clock, output (pin 116) on the EEPROM interface.
REGB[21] (Write-Only)
Control the EECS, chips select, output (pin 115) to the EEPROM device.
REGB[22] (Write-Only)
EEDI (pin 114) data input. Write data to the EEPROM device.
REGB[23] (Read-Only)
EEDO (pin 113) data output. Read data from the EEPROM device.
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