XRT86VL34_2 Datasheet, PDF (66/156 Pages) Exar Corporation – QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

XRT86VL34
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 44: RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR2)
HEX ADDRESS: 0Xn145
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 RBUFPTR
R/W
0
Receive HDLC2 Buffer-Pointer
This bit Identifies which Receive HDLC2 buffer contains the most
recently received HDLC2 message.
0 - Indicates that Receive HDLC2 Buffer # 0 contains the contents of
the most recently received HDLC message.
1 - Indicates that Receive HDLC2 Buffer # 1 contains the contents of
the most recently received HDLC message.
6-0 RDLBC[6:0]
R/W 0000000 Receive HDLC Message - byte count
The exact function of these bits depends on whether the Receive
HDLC Controller Block #2 is configured to receive MOS or BOS
messages.
In BOS Mode:
These seven bits contain the number of repetitions the BOS mes-
sage must be received before the Receive HDLC2 controller gener-
ates the Receive End of Transfer (RxEOT) interrupt. If these bits are
set to “0000000”, the message will be received indefinitely and no
Receive End of Transfer (RxEOT) interrupt will be generated.
In MOS Mode:
These seven bits contain the size in bytes of the HDLC2 message
that has been received and written into the Receive HDLC buffer.
The length of MOS message shown in these bits include header
bytes such as the SAPI, TEI, Control field, AND the FCS bytes.
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