XRT86VL34_2 Datasheet, PDF(54/156 Page) Exar Corporation – QUAD T1/E1/J1 FRAMER/LIU COMBO

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XRT86VL34_2 Datasheet, PDF (54/156 Pages) Exar Corporation – QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

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XRT86VL34

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 32: RECEIVE INTERFACE CONTROL REGISTER (RICR)

REV. V1.2.0

HEX ADDRESS: 0XN122

BIT

FUNCTION

TYPE DEFAULT

DESCRIPTION-OPERATION

4 RxFr1544

R/W

Receive Fractional/Signaling Interface Enabled

This bit is used to enable or disable the receive fractional output interface,

receive signaling output, the serial channel number output, as well as the

8kHz and the received recovered clock output. This bit only functions when

the device is configured in non-high speed or multiplexed modes of opera-

tions.

If the device is configured in base rate:

0 = Configures the 5 time slot identifier pins (RxChn[4:0]) to output the chan-

nel number in parallel as usual.

1 = Configures the 5 time slot identifier pins (RxChn[4:0]) into the following dif-

ferent functions:

RxChn[0] becomes the Receive Serial SIgnaling output pin (RxSIG_n) for sig-

naling outputs. Signaling data can now be output to the RxSIG pin if config-

ured appropriately.

RxChn[1] becomes the Receive Fractional Data Output pin (RxFrTD_n) for

fractional data output. Fractional data can now be output to the RxFrTD pin if

configured appropriately.

RxChn[2] outputs the serial channel number

RxChn[3] outputs an 8kHz clock signal.

RxCHN[4] outputs the received recovered clock signal (1.544MHz for T1)

NOTE: This bit has no effect in the high speed or multiplexed modes of

operation. In high-speed or multiplexed modes, RxCHN[0] outputs the

Signaling data and RxCHN[4] outputs the recovered clock.

3 RxICLKINV

N/A

Receive Clock Inversion (Backplane Interface)

This bit selects whether data transition will happen on the rising or falling edge

of the receive clock.

0 = Selects data transition to happen on the rising edge of the receive clocks.

1 = Selects data transition to happen on the falling edge of the receive clocks.

NOTE: This feature is only available for base rate configuration (i.e. non-

highspeed, or non-multiplexed modes).

2 RxMUXEN

R/W

Receive Multiplexed Mode Enable

This bit enables or disables the multiplexed mode on the receive side. When

multiplexed mode is enable, data of four channels from the line side are multi-

plexed onto one serial stream inside the receive framer and output to the

back-plane interface on RxSER. The backplane speed will become either

12.352MHz or 16.384MHz once multiplexed mode is enabled.

0 = Disables the multiplexed mode.

1 = Enables the multiplexed mode.

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