XRS10L210 Datasheet, PDF (6/37 Pages) Exar Corporation – SERIAL ATA II: PORT SELECTOR

EXSTOR - 1 XRS10L210
SERIAL ATA II: PORT SELECTOR
TABLE 1: XRS10L210 PIN DESCRIPTIONS
REV. 1.04
PIN NAME
QFN 64
LQFP
PIN
100 PIN _NUMBER
I/O
NUMBER
(NOTE 1)
TYPE
DESCRIPTION
PWRDNB
52
31
I
LVCMOS Active low power down signal for chip, +3.3V LVC-
MOS.
DRACT
HBACT
74
44
O
LVCMOS Drive activity port for external LED. Active Low,
3.3V LVCMOS, open drain
76
46
O
LVCMOS 0 = Host 0 selected (status)
1 = No host selected (status)
0-1-0-1 Toggle = Host 1 selected (1 sec stay at
each state)
3.3V LVCMOS
PS_SIDEBAND_
77
47
I
LVCMOS +3.3V LVCMOS
B
Please refer to Table 2, “Host Port Selec-
tion,” on page 8
PORTSEL
2
7
I
LVCMOS Port selector external input pin when this mode is
set in the register. Low selects host port 0, other-
wise port 1. +3.3V LVCMOS
TEST PIN
ANTEST
CLKSTN/
CLKSTP
NC
51
24, 25
30
16, 17
7, 8, 10,
11, 13,
14, 16,
17, 19,
20, 27,
28, 30,
31, 33,
34, 35,
36, 37,
39, 40,
56, 57,
59, 60,
71, 72
O
Analog Analog test pin
O
CML Output clock test pin
AC
Coupled
RESERVED PINS
No Connect - Do not connect this pin during oper-
ational use.
SCANMODE
41
20
TMODE
73
43
I
LVCMOS For factory use only, connect to ground.
For factory use only, leave floating. Do not con-
nect this pin during operational use.
POWER AND GROUND SIGNALS
6