XRS10L210 Datasheet, PDF (5/37 Pages) Exar Corporation – SERIAL ATA II: PORT SELECTOR

REV. 1.04
2.0 PIN DESCRIPTIONS
EXSTOR - 1 XRS10L210
SERIAL ATA II: PORT SELECTOR
TABLE 1: XRS10L210 PIN DESCRIPTIONS
PIN NAME
QFN 64
LQFP
PIN
100 PIN _NUMBER
I/O
NUMBER
(NOTE 1)
TYPE
DESCRIPTION
DATA INTERFACE
SOTP/SOTN
68, 69 40. 41
CML Serial ATA Output Transmitters. These ports com-
O
AC
municate from the XRS10L210 to downstream
Coupled ^devices
SORP/SORN
65, 66 37, 38
I
Serial ATA Input Receivers. These ports receive
signals from downstream devices
SITP0/SITN0
93, 94 63, 64
SITP1/SITN1
82, 81 52, 51
O
Serial ATA Output Transmitters. These ports com-
municate from the XRS10L210 to upstream hosts.
SIRP0/SIRN0
90, 91 60, 61
I
SIRP1/SIRN1
85, 84 55, 54
Serial ATA Input Receivers. These ports receive
signals from upstream hosts.
CLOCK INTERFACE
CMU_REFP/
46,
25, 26
I
CMU_REFN
47
CML
AC
Reference clock input
Coupled
XOD
43
22
0
Analog Crystal oscillator output
XOG
44
23
I
Analog Crystal oscillator input, 1.26V max
MDIO INTERFACE SIGNALS
MDC
3
8
I
LVCMOS MDIO clock input, +3.3V LVCMOS
MDIO
5
10
I/O
LVCMOS MDIO data port, +3.3V LVCMOS. Open drain
JTAG INTERFACE SIGNALS
TCK
96
2
I
LVCMOS JTAG test clock, +3.3V LVCMOS
TDI
100
5
I
JTAG test data in, +3.3V LVCMOS
TDO
99
4
O
JTAG test data out, +3.3V LVCMOS. Open drain If
used to daisy chain JTAG devices, pull up exter-
nally using 3.3KOhm resistor.
TMS
97
3
I
JTAG mode select, +3.3V LVCMOS
TRST
1
6
I
JTAG test reset, +3.3V LVCMOS. Pull low exter-
nally using 3.3KOhm resistor for normal operation
of the device.
GENERAL CONTROL AND CONFIGURATION SIGNALS (CMOS)
RBIAS
49
28
I
Analog Connection point for calibration termination resis-
tor.
RESETB
75
45
I
LVCMOS Active low reset pin, +3.3V LVCMOS.
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