XR88C192IV-F Datasheet, PDF (6/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR88C92/192
SYMBOL DESCRIPTION (* 44 pin LQFP)
Symbol
IP3
IP4
IP5
IP6
-CS
Pin
Signal
44
44* type
Pin Description
3
41
I Multi-purpose input or Channel A transmit external clock port
input. The transmit data is clocked on the falling edge of the
clock.
43
37
I Multi-purpose input or Channel A receive external clock input.
The transmit data is clocked on the rising edge of the clock.
42
36
I Multi-purpose input or Channel B Transmit external clock
input. The transmit data is clocked on the falling edge of the
clock.
41
35
I Multi-purpose input or Channel B receive external clock input.
The transmit data is clocked on the rising edge of the clock.
39
33
I Chip select (active low). A low at this pin enables the serial
port / CPU data transfer operation.
D0-D7
28,18
27,19
26,20
25,21
22,12
Bi-directional data bus. Eight bit, three state data bus to
21,13 I/O transfer information to or from the CPU. D0 is the least
20,14
significant bit of the data bus and the first serial data bit to be
19,15
received or transmitted.
-IOW
-IOR
VCC
N.C.
9
10
44
1,12
23,34
3
I Write strobe (active low). A low on this pin will transfer the
contents of the CPU data bus to the addressed register.
4
I Read strobe (active low). A low on this pin will transfer the
contents of the XR88C92/192 register to CPU data bus.
38,39 Pwr Power supply input, 2.97V to 5.5V.
11,23
No Connection.
Rev. 1.33
6