XR88C192IV-F Datasheet, PDF (3/32 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

Block Diagram
D0-D7
-IOR
-IOW
RESET
A0-A3
-CS
-INT
XTAL1
XTAL2
Rev. 1.33
XR88C92/192
Channel A
Transmit
FIFO
Registers
Transmit
Shift
Register
Flow
Control
Logic
Receive
FIFO
Registers
Receive
Shift
Register
Flow
Control
Logic
Watch
Dog
Timer
Channel B
Transmit
FIFO
Registers
Transmit
Shift
Register
Flow
Control
Logic
Receive
FIFO
Registers
Flow
Control
Logic
Receive
Shift
Register
Watch
Dog
Timer
Multi-
Purpose
I/O
Control
Logic
TXA
RXA
TXB
RXB
OP0-OP7
IP0-IP6
3