XR19L200 Datasheet, PDF (6/40 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L200
PRELIMINARY
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. P1.0.2
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L200 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR19L200 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CS#
UART_INT
UART_RESET
ACP
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
VCC
R/W#
4.7K
UART_IRQ#
UART_CS#
UART_RESET#
ACP
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CS#
INT
RESET
ACP
VCC
16/68#
TX
RX
VCC
RS-232
Interface
GND
Intel Data Bus Interconnections
VCC
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CS#
INT
RESET
ACP
VCC
TX
RX
VCC
RS-232
Interface
16/68#
GND
Motorola Data Bus Interconnections
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