XR19L200 Datasheet, PDF (23/40 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

REV. P1.0.2
PRELIMINARY
XR19L200
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
MCR[1]: RTS# Output
The RTS# output is not available as an output on this device. But for 16C550 compatibility, it can still be used
in internal loopback mode.
• Logic 0 = Force RTS output HIGH (default).
• Logic 1 = Force RTS output LOW.
MCR[2]: OP1# (legacy term)
The OP1# output is not available on the XR19L200, however, it is available in internal loopback. In the Internal
Loopback Mode, this bit controls the state of the modem input RI bit in the MSR register as shown in Figure 9.
• Logic 0 = OP1# is HIGH (default).
• Logic 1 = OP1# is LOW.
In the Internal Loopback Mode, this bit controls the state of the modem input RI bit in the MSR register as
shown in Figure 9.
MCR[3]: INT Output Enable or OP2# (legacy term)
This bit enables and disables the operation of interrupt output, INT in the Intel mode. If INT output is not used,
OP2# can be used as a general purpose output in the Intel mode. In the Motorola mode, this bit must be set to
logic 0.
• Logic 0 = INT output disabled (three state mode) in Intel mode (default).
• Logic 1 = INT output enabled (active mode) in Intel mode.
In the Internal Loopback Mode, this bit functions like the OP2# in the 16C550 and is used to set the state of the
modem input CD bit in the MSR register.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 9.
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the L200 is programmed to use the Xon/Xoff flow control.
MCR[6]: Reserved
For proper functionality, this bit should be set to a logic 0.
MCR[7]: BRG Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates get reduced 4 times.
4.9 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
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