XR16M581 Datasheet, PDF (6/51 Pages) Exar Corporation – 1.62V TO 3.63V UART WITH 16-BYTE FIFO AND VLIO INTERFACE

XR16M581
1.62V TO 3.63V UART WITH 16-BYTE FIFO AND VLIO INTERFACE
REV. 1.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is a VLIO bus interface. The VLIO bus interface is an 8-bit multiplexed address/data bus
interface. Each bus cycle is asynchronous using CS#, LLA# and IOR# or IOW# inputs. A typical data bus
interconnection for the VLIO bus interface is shown in Figure 3.
FIGURE 3. XR16M581 TYPICAL VLIO DATA BUS INTERCONNECTIONS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
UART_IOR#
UART_IOW#
UART_CS#
UART_INT
POWERSAVE
UART_RESET#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
IOR#
IOW#
CS#
INT
PWRSAVE
RESET#
VCC
VCC
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
GND
Serial Transceivers of
RS-232
RS-485
RS-422
Or Infrared
6