XRT73L06 Datasheet, PDF (54/63 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73L06
REV. 1.0.2
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMOIE_n If the Driver Monitor (connected to the output of the
0
channel) detects the absence of pulses for 128 con-
secutive cycles, it will set the interrupt flag if this bit
has been set.
D1 RLOSIE_n This flag will allow a loss of receive signal(for that
0
0x01 (ch 0) R/W Interrupt
0x11 (ch 1)
Enable
channel) to send an interrupt to the Host when this
bit is set.
0x21 (ch 2)
0x31 (ch 3)
0x41 (ch 4)
(source
level)
D2 RLOLIE_n This flag will allow a loss of lock condition to send an
0
interrupt to the Host when this bit is set.
0x51 (ch 5)
D3 Reserved ^{This bit is Reserved.}
0
D4 PRBSERIE Set this bit to enable the interrupt when the PRBS
0
_n
error is detected.
D5 PRBSERC Set this bit to enable the interrupt when the PRBS
0
NTIE_n error count register saturates.
D6-D7
Reserved
D0 DMOIS_n If the Drive monitor circuot detects the absence of
0
pulses for 128 consecutive cycles, t will set this
interrupt status flag (if enabled) This bit is set on a
change of state of the DMO circuit.
D1 RLOSIS_n This flag will indicate a change of “loss of Receive
0
0x02 (ch 0) Reset Interrupt
signal” to the Host when this bit is set.
0x12 (ch 1)
0x22 (ch 2)
0x32 (ch 3)
0x42 (ch 4)
0x52 (ch 5)
on Status
Read (source
level)
D2 RLOLIS_n This flag will allow a change in the loss of lock condi-
0
tion to send an interrupt to the Host when this bit is
enabled.Loss of lock is defined as a difference of
greater than 0.5% between the recovered clock and
the channel’s reference clock. Any change (return to
lock) will trigger the interrupt status flag again.
D3 Reserved ^{This bit is Reserved.}
0
D4 PRBSERIS This bit is set when the PRBS error occurs.
0
_n
D5 PRBSERC This bit is set when the PRBS error count register
0
NTIS_n saturates.
D7-D6
Reserved
51