XR21B1420 Datasheet, PDF (53/60 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed USB UART

XR21B1420
Bit
6
5:2
1:0
Default
Description
0
PULLDOWN_EN
This register bit is used to enable the internal pull-down resistor. This setting will be ignored if GPIO0/RI#/RWK#
is configured as an output.
0: Do not enable internal pull-down
1: Enable internal pull-down if configured as an input (will not be enabled if Pull up is enabled)
0
RESERVED
These bits are reserved and should be written as ’0’.
0
CTRL
00: GPIO0/RI#/RWK# is configured as a GPIO input
01: GPIO0/RI#/RWK# is configured as a GPIO open drain output
10: GPIO0/RI#/RWK# is configured as a GPIO push-pull output
11 to 111: Invalid, do not use
PIN_CFG_DTR (0x02C) - Read/Write OTP
This register configures the functionality of the GPIO3/DTR pin
Bit
7
6
5:3
2:0
Default
Description
0
PULLUP_EN
This register bit is used to enable the internal pull-up resistor. This setting will be ignored if GPIO3/DTR# is con-
figured as an output.
0: Do not enable internal pull-up
1: Enable internal pull-up if configured as an input
0
PULLDOWN_EN
This register bit is used to enable the internal pull-down resistor. This setting will be ignored if GPIO3/DTR# is
configured as an output.
0: Do not enable internal pull-down
1: Enable internal pull-down if configured as an input (will not be enabled if Pull up is enabled)
0
RESERVED
These bits are reserved and should be written as ’0’.
0
CTRL
Note: If configured as DTR output, GPIO2/DSR# must be configured as DSR input and GPIO5/RTS#/RS485
and GPIO4/CTS# must be configured as GPIOs.
000: GPIO3/DTR is configured as a GPIO input
001: GPIO3/DTR is configured as a GPIO open drain output
010: GPIO3/DTR is configured as a GPIO push-pull output
011: GPIO3/DTR is configured as a open drain DTR output
100: GPIO3/DTR is configured as a push-pull DTR output
101 to 111: Invalid, do not use
© 2014 Exar Corporation
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Rev 1A