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XR21B1420 Datasheet, PDF (10/60 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed USB UART
XR21B1420
Self-Powered 3.3V
In self-powered 3.3V mode, a local source provides 3.3V to both the VCC_REG and VCC pins of the XR21B1420 device.
The USB attributes should be changed in the OTP to correctly report self-powered mode.
3.3V
Supply
VBUS
Dp
Dm
GND
USB Connector
XR21B1420
VCC_REG
VBUS_SENSE
Dp
Dm
GND
VCC
Figure 3: Self-Powered 3.3V Mode
Reset
The XR21B1420 has three different types of resets: power-on reset or POR, hardware reset, and USB bus reset. The
results of each of the three types of resets are listed in Table 3.
Table 3: Device Resets
Reset Type
Power On Reset
(POR)
Hardware Reset
USB Bus Reset
Device Actions
Resets all registers and pins to default states including any OTP mod-
ifications. Locks OTP from further writes if Global Lock is set.
Resets all registers and pins to default states including any OTP mod-
ifications. Locks OTP from further writes if Global Lock is set.
Resets USB Interface, re-enumerate device, reset all internal states,
clear UART FIFOs. Does not reset registers or pin configurations.
UART
The UART may be configured via USB control transfers from the USB host. The UART transmitter and receiver sections are
described separately in the following sections. At power-up, the XR21B1420 will default to 115.2 kbps, 8 data bits, no parity
bit, 1 stop bit, and no flow control. If a standard CDC driver accesses the XR21B1420, these defaults will be changed. See
“Device Driver” on page 8.
Transmitter
The transmitter consists of a 512-byte TX FIFO and a Transmit Shift Register (TSR). Once a Set transmit data interrupt out
or bulk-out packet has been received and the CRC has been validated, the data bytes in that packet are written into the TX
FIFO. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data
byte. The TSR shifts the data out onto the TX output pin at the selected baud rate. The transmitter sends the start bit fol-
lowed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds the stop-bit(s). The transmit-
ter may be configured for 5, 6, 7 or 8 data bits with or without parity or 9 data bits without parity. If 5, 6, 7 or 8 bit data with
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Rev 1A