XR21B1420 Datasheet, PDF (14/60 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed USB UART

Figure 6: Auto RTS and CTS Flow Control Operation
XR21B1420
Automatic DTR/DSR Hardware Flow Control
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control described above
except that it uses the DTR# and DSR# signals. GPIO2 and GPIO3 become DSR# and DTR#, respectively, when the GPI-
O_MODE register is configured for DTR/DSR hardware flow control.
Automatic XON/XOFF Software Flow Control
When software flow control is enabled, the XR21B1420 compares the receive data characters with the programmed XON or
XOFF characters. If the received character matches the programmed XOFF character, the XR21B1420 will halt transmis-
sion as soon as the current character has completed transmission. Data transmission is resumed when a received charac-
ter matches the XON character.
In the receive data direction, the XOFF character will be sent when there are 450 bytes in the receive FIFO. When there are
again less than 450 bytes in the RX FIFO, the XON character will be sent. This threshold may be changed using the RX_-
THRESHOLD register.
Software flow control is enabled / disabled by the FLOW_CONTROL register. Additionally, the XON_CHAR and
XOFF_CHAR registers may be used to configure the start (XON) and stop (XOFF) characters.
Multidrop mode with address matching
The XR21B1420 device has two address matching modes which are set by the FLOW_CONTROL and GPIO_MODE regis-
ters. These modes are intended for use in a multi-drop network application. Address matching may be used with any size
data character, as well as with and without parity. An address match occurs when the last (most significant) received data
bit or the parity bit, if there is one, is a ’1’ and the address matches the value stored in either the XON_CHAR or
XOFF_CHAR register. To send an address byte use 5, 6, 7, 8 or 9 bit data with either the most significant data bit a ’1’ or if
parity is used, set mark parity. To send data bytes, the most significant data bit must be a ’0’ or use space parity.
Receiver
If an address match occurs in either of the address matching modes, the address byte and all subsequent data bytes will be
loaded into the RX FIFO. The UART Receiver will automatically be disabled when an address byte is received that does not
match the values in the XON_CHAR or XOFF_CHAR characters.
Transmitter
In flow control mode 3, the UART transmitter will transmit irrespective of the RX address match. In flow control mode 4, the
UART will only transmit following an RX address match.
Programmable Turn-Around Delay
By default, the selected RS-485 half-duplex enable pin (either GPIO7/RS485 or GPIO5/RTS#/RS485) will be de-asserted
immediately after the stop bit of the last byte has been shifted. However, this may not be ideal for systems where the signal
needs to propagate over long cables. Therefore, the de-assertion of the RS-485 half-duplex enable can be delayed from 1
to 15 bit times via the XCVR_EN_DELAY register to allow for the data to reach distant UARTs.
UART Half-Duplex Mode
In UART half-duplex mode, the UART will ignore any data on the RX input when the UART is transmitting data. The half-
duplex mode can be configured using the FLOW_CONTROL register.
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