XRT73R12_0710 Datasheet, PDF (52/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.3
NOTE: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access
time, use the following formula: (PCLK_period * 2) + 5ns
7.3 Register Map
TABLE 17: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT73R12
ADDRESS
(HEX)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
REGISTER NAME
CR0
APST R/W APS Transmit Redundancy Control Register 0-5
CHANNEL 0 CONTROL REGISTERS
CR1
IER0 R/W Source Level Interrupt Enable Register - Ch 0
CR2
ISR0 RUR Source Level Interrupt Status Register Ch 0
CR3
AS0
R/O Alarm Status Register - Ch 0
CR4
TC0
R/W Transmit Control Register - Ch 0
CR5
RC0
R/W Receive Control Register - Ch 0
CR6
CC0
R/W Channel Control Register - Ch 0
CR7
Reserved
CR8
APSR R/W APS Receive Redundancy Control Register 0-5
CR10
CR11
CR12
EM0
EL0
EH0
R/W Error counter MS Byte Ch 0
R/W Error counter LS Byte
R/W Error counter Holding register
CR17
CR18
CR19
CR20
CR21
CR22
CR23
CHANNEL 1 CONTROL REGISTERS
IER1 R/W Source Level Interrupt Enable Register - Ch 1
ISR1 RUR Source Level Interrupt Status Register - Ch 1
AS1
R/O Alarm Status Register - Ch 1
TC0
R/W Transmit Control Register - Ch 1
RC1
R/W Receive Control Register - Ch 1
CC1
R/W Channel Control Register - Ch 1
Reserved
CR26
EM1
R/W Error counter MSByte Ch 1
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