XRT73R12_0710 Datasheet, PDF (24/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.3
3.0 THE RECEIVER SECTION
The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by
cable loss or flat loss according to industry specifications. Once data is recovered, it is processed and
presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC.
This section describes the detailed operation of various blocks within the receive path. A simplified block
diagram of the receive path is shown in Figure 5.
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM
RTIP_n
RRing_n
Peak Detector
AGC/
Equalizer
Slicer
Clock & Data
Recovery
LOS
Detector
HDB3/
MUX
B3ZS
Decoder
Channel n
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
3.1 Receive Line Interface
Physical Layer devices are AC coupled to a line interface through a 1:1 transformer. The transformer provides
isolation and a level shift by blocking the DC offset of the incoming data stream. The typical medium for the
line interface is a 75Ω coxial cable. Whether using E3, DS-3 or STS-1, the LIU requires the same bill of
materials, see Figure 6.
FIGURE 6. RECEIVE LINE INTERFACECONNECTION
1:1
Receiver
DS-3/E3/STS-1
37.5Ω
37.5Ω
RLOS_n
0.01µF
RTIP_n
75Ω
RRing_n
3.2 Adaptive Gain Control (AGC)
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak
detector provides feedback to the equalizer before slicing occurs.
3.3 Receive Equalizer
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of
up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the
signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to
generate Positive and Negative data. The equalizer can be disabled by programming the appropriate register.
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