XR16V2751_0709 Datasheet, PDF (52/52 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE

XR16V2751
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.1
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 24
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 25
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 25
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 26
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 26
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 26
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 27
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 27
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 29
TABLE 12: PARITY SELECTION ........................................................................................................................................................ 30
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 30
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 32
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 32
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 33
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ......................................................................................... 33
TABLE 13: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 34
TABLE 14: AUTO RTS HYSTERESIS ................................................................................................................................................ 34
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY............................................................................................. 35
4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 35
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 35
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ................................................................................. 35
4.16 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY .................................................................................... 35
4.17 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 35
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE........................................................................... 35
TABLE 15: TRIGGER TABLE SELECT ................................................................................................................................................ 36
4.19 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 36
TABLE 16: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37
4.19.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 38
TABLE 17: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 39
ABSOLUTE MAXIMUM RATINGS.................................................................................. 40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 40
ELECTRICAL CHARACTERISTICS ............................................................................... 40
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 40
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.25V to 3.6V ............................................. 40
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 41
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25 - 3.63V, 70 pF load
where applicable....................................................................................................................................................... 41
FIGURE 13. CLOCK TIMING............................................................................................................................................................. 42
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 43
FIGURE 15. 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 43
FIGURE 16. 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 44
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 44
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 45
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 45
FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 46
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 46
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 47
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 47
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 48
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................................................... 49
REVISION HISTORY...................................................................................................................................... 50
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