XR16V2751_0709 Datasheet, PDF (51/52 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.0.1
XR16V2751
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
APPLICATIONS .............................................................................................................................................. 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. XR16V2751 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION .............................................................................................................................. 2
PIN DESCRIPTIONS ........................................................................................................ 3
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8
2.1 CPU INTERFACE ................................................................................................................................................ 8
FIGURE 3. XR16V2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS........................................................................... 8
2.2 5-VOLT TOLERANT INPUTS .............................................................................................................................. 8
2.3 DEVICE RESET ................................................................................................................................................... 9
2.4 DEVICE IDENTIFICATION AND REVISION ....................................................................................................... 9
2.5 CHANNEL A AND B SELECTION ...................................................................................................................... 9
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE ............................................................................................................................ 9
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE ............................................................................................................................ 9
2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................... 9
2.7 DMA MODE ....................................................................................................................................................... 10
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ........................................................................................... 10
2.8 INTA AND INTB OUTPUTS............................................................................................................................... 10
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 10
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 10
2.9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 11
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 11
2.10 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ......................................... 11
FIGURE 5. BAUD RATE GENERATOR ............................................................................................................................................... 12
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 13
2.11 TRANSMITTER................................................................................................................................................ 13
2.11.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 14
2.11.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 14
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 14
2.11.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 14
FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14
2.12 RECEIVER ....................................................................................................................................................... 15
2.12.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 15
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 15
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ......................................................................... 16
2.13 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 16
2.14 AUTO RTS HYSTERESIS .............................................................................................................................. 16
2.15 AUTO CTS FLOW CONTROL........................................................................................................................ 17
FIGURE 10. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 17
2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 18
TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 18
2.17 SPECIAL CHARACTER DETECT.................................................................................................................. 18
2.18 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 18
2.19 INFRARED MODE ........................................................................................................................................... 19
FIGURE 11. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 19
2.20 SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE FEATURE ............................................ 20
2.20.1 SLEEP MODE ............................................................................................................................................................. 20
2.20.2 POWERSAVE FEATURE............................................................................................................................................ 20
2.21 INTERNAL LOOPBACK................................................................................................................................. 21
FIGURE 12. INTERNAL LOOPBACK IN CHANNEL A AND B.................................................................................................................. 21
3.0 UART INTERNAL REGISTERS............................................................................................................. 22
TABLE 8: UART INTERNAL REGISTERS .......................................................................................................................................... 22
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 .................................................... 23
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 24
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