XRT73L03A Datasheet, PDF (51/62 Pages) Exar Corporation – 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X STS-1/DS3_(n)
E3_(n) LLB_(n) RLB_(n)
X
X
X
1
0
b. Operating in the Hardware Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB_(n) input pin “High"
and the RLB_(n) input pin "Low".
4.2 THE DIGITAL LOCAL LOOP-BACK MODE.
When a given channel is configured to operate in the
Digital Local Loop-Back Mode, the channel ignores
any signals that are input to the RTIP and RRing input
pins. The Transmitting Terminal Equipment transmits
clock and data into the XRT73L03A via the TPData,
TNData and TxClk input pins. This data is processed
through the Transmit Clock Duty Cycle Adjust PLL
and the HDB3/B3ZS Encoder block. At this point, this
data is looped back to the HDB3/B3ZS Decoder
block. After this post-Loop-Back data has been pro-
cessed through the HDB3/B3ZS Decoder block, it
outputs to the Near-End Receiving Terminal Equip-
ment via the RPOS, RNEG and RxClk output pins.
Figure 35 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
FIGURE 35. THE DIGITAL LOCAL LOOP-BACK PATH WITHIN A GIVEN CHANNEL
RLOL_(n) EXClk_(n)
RTIP_(n)
RRing_(n)
REQEN_(n)
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
TTIP_(n)
TRing_(n)
TxLEV_(n)
TxOFF_(n)
DMO_(n)
AGC/
Equalizer
Slicer
Clock
Recovery
Serial
Processor
Interface
Peak
Detector
LOS Detector
Digital Local
Loop-Back Path
Data
Recovery
Loop MUX
Invert
HDB3/
B3ZS
Decoder
Pulse
Shaping
HDB3/
B3ZS
Encoder
Device
Monitor
Transmit
Logic
Duty Cycle Adjust
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV(_n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData(_n)
TNData_(n)
TxClk_(n)
MTIP_(n)
MRing(_n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
Configure a channel to operate in the Digital Local
Loop-Back Mode by employing either one of the fol-
lowing two-steps:
a. Operating in the Host Mode
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, write a "1" into both the LLB
and RLB bit-fields within Command Register CR4-(n).
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X STS-1/DS3_(n) E3_(n) LLB_(n) RLB_(n)
X
X
X
1
1
b. Operating in the Hardware Mode.
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