XR16C864 Datasheet, PDF (51/51 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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REV. 2.0.1
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 25
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 25
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 27
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 29
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 29
TABLE 12: PARITY SELECTION ........................................................................................................................................................ 30
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 31
TABLE 13: INT OUTPUT MODES ..................................................................................................................................................... 31
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 32
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 33
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 34
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 34
TABLE 14: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 34
TABLE 15: AUTO RTS HYSTERESIS ............................................................................................................................................... 35
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ......................................................................................... 35
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 35
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 35
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 35
4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ..................................................................................................... 35
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY ................................................................................. 36
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ....................................................................... 36
4.19 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................ 36
TABLE 16: TRIGGER TABLE SELECT ............................................................................................................................................... 36
TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 38
4.21 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 38
TABLE 18: UART RESET CONDITIONS FOR CHANNELS A-D ................................................................................................. 39
ELECTRICAL CHARACTERISTICS................................................................................ 40
ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) ................................................ 40
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 40
AC ELECTRICAL CHARACTERISTICS.............................................................................................................. 41
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V ........................ 41
FIGURE 13. CLOCK TIMING............................................................................................................................................................. 42
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 42
FIGURE 15. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D ................................................................................... 43
FIGURE 16. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 43
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 44
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 44
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 45
FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 45
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 46
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 46
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D .............................. 47
PACKAGE DIMENSIONS................................................................................................................................. 48
REVISION HISTORY ...................................................................................................................................... 49
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